A semiconductor fabrication facility uses “masks” to create physical layers of material on a semiconductor wafer. Traditionally, the semiconductor fabrication facility uses one mask per physical layer to place/remove material on/from the semiconductor wafer. The material may be conductive (e.g., metal or polysilicon) or non-conductive based upon the purpose of each particular physical layer.
Masks are created from design layouts, which geometrically specify “open areas” on a particular physical layer for which to place/remove material. A design layout includes “objects” corresponding to component objects, such as a transistor gate, and connection objects (e.g., routes) that connect a component's output to a component's input. When a mask is created from the design layout, the masks include open areas corresponding to the component objects and connection objects included in the design layout. As such, when the mask is used in a semiconductor fabrication process, material is placed in the open areas on the semiconductor wafer.
In the process of creating connection objects, design layout tools may use “maze routing” algorithms to generate several “possible connection routes” (e.g., possible connection “paths”) between a source grid point and a target grid point and, in turn, back track the “best” possible connection route to generate the connection object. Using this approach, the design layout tool partitions the design layout into a grid of “grid points” and performs a maze expansion, starting at the source grid point, until the maze search reaches a target grid point. The size of each grid point typically corresponds to a minimal spacing requirement of the semiconductor technology on which the resulting masks will be utilized.
Minimal spacing capabilities of advanced semiconductor technology processes, however, decrease a design layout's grid point sizing to a point at which a single mask may not able to achieve optimal routing densities due to photoresist pattern resolution limitations used with the masks. In other words, a single mask may not be able to place material on a semiconductor wafer corresponding to two objects in a design layout residing on adjacent grid points (“near” each other).
As such, “double patterning” was developed that utilizes two separate masks to create a single physical layer on a semiconductor wafer, thus allowing a semiconductor fabrication facility to produce minimum pitch features on the physical layer. Using a double patterning approach, a first mask is used to lay down a first set of material and a second mask is subsequently used to lay down a second set of material that is near the first set of material.
In certain situations (e.g., densely populated areas), a design layout tool that implements double patterning aware routing methods allows a segment of a connection object to be assigned to one mask, and another segment of the same connection object to be assigned to a different mask. In these situations, once the two masks are used to lay down two segments of material corresponding to the two segments of the connection object, the semiconductor fabrication facility “stitches” together the two segments of material with more material to complete the connection.
Some manufacturing facilities, however, do not support stitching as part of their semiconductor fabrication process. As such, the current double patterning routing methods may not create implementable double patterning masks.